(a). Field of the Invention
The present invention relates to integrated circuits, and more particularly to an integrated circuit with a low temperature coefficient and an associated calibration method.
(b). Description of the Prior Arts
When designing an integrated circuit, it is desirable for the integrated circuit to have a low temperature coefficient such that the effect of the environmental temperature can be lowered to upgrade the stability and reliability of the integrated circuit. The temperature coefficient is typically denoted by the unit of ppm (i.e. parts per million), and used to indicate the variation amount of a circuit parameter (e.g. voltage, current, frequency, etc.) resulted from temperature variation. The larger/smaller variation amount of the circuit parameter means the higher/lower temperature coefficient. In particular, the effect of the temperature variation is much more evident for the system comprised of integrated circuits, e.g. the System on Chip (SoC) which is widely developed and used nowadays. However, to lower the temperature coefficient of each sub-circuit within the integrated circuit would increase the circuit complexity, and thus increase both the area and power consumption of the integrated circuit. In this situation, the cost would also be increased substantially.